Raspberry Pi /RP2350 /CORESIGHT_TRACE /TRACE_CAPTURE_FIFO

Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU.

Hardware pushes to the FIFO on rising edges of clk_sys, when either of the following is true:

• TPIU TRACECTL output is low (normal trace data)

• TPIU TRACETCL output is high, and TPIU TRACEDATA0 and TRACEDATA1 are both low (trigger packet)

These conditions are in accordance with Arm Coresight Architecture Spec v3.0 section D3.3.3: Decoding requirements for Trace Capture Devices

The data captured into the FIFO is the full 32-bit TRACEDATA bus output by the TPIU. Note that the TPIU is a DDR output at half of clk_sys, therefore this interface can capture the full 32-bit TPIU DDR output bandwidth as it samples once per active edge of the TPIU output clock.